Geometry
Top view (left) and isometric view (right) of the placed-and-routed chip. Rendered with OpenSCAD from the chip’s SCAD source, smart_toilet_base.scad. Click for high-resolution.
Download: PNG (top) · PNG (iso) · SCAD source ↓
Specifications
Description
Three-input passive resistance-metered chip for calcium quantification by the Arsenazo III method. Pure serpentine-channel metering — no pumps or valves. Mixing ratio 2:25:225 (sample : arsenazo : dilution).
Assay
This chip is designed to measure urinary calcium concentration via the Arsenazo III colorimetric reaction. Arsenazo III dye binds Ca2+ in acidic conditions to form a purple/violet complex whose absorbance (typically read at 650 nm) is proportional to the calcium concentration in the original sample.
Clinically, urinary calcium quantification supports kidney stone risk screening and mineral metabolism studies. This is the chemistry characterised in Tazin et al. 2022; in Goenner et al. 2025 a chip for it ran end-to-end through the OpenMFDA pipeline, as the paper’s calcium-quantification case study. This design carries that case study’s name, but nothing here shows that it is the exact layout used in the paper. It is the methodology archetype the Gale Lab urinalysis chip family is built on.
The chip implements purely passive resistance-metering: three input streams (sample, Arsenazo III reagent, dilution buffer) are combined at a fixed 2:25:225 ratio via 14 serpentine-channel flow resistors and two diffmix_25px_0 junctions, then exit through a single output channel for off-chip spectrophotometric readout.
Components used (4)
The cells the netlist names. The chip’s .scad draws them with the design software’s own library, inlined in it.
Files
- SCAD
smart_toilet_base.scad190.8 KBDownload - VERILOG
smart_toilet.v1.5 KBDownload - CONFIG
config.mk881 BDownload - IO
io_constraints.tcl2.8 KBDownload - SIM
simulation.config802 BDownload - CONSTRAINT
constraint.sdc27 BDownload - PLACE
global_place_args.tcl1.6 KBDownload - PNG
smart_toilet_iso_large.png169.1 KBDownload - PNG
smart_toilet_top_large.png21.8 KBDownload
smart_toilet_base.scad is the placed-and-routed 3D geometry — the main OpenSCAD source for this chip, as the design software makes it from the netlist and the input files beside it, at commit 63d1e54 of the public openmfda_flow repository; the library it was laid out with is inlined, so it opens on its own. The netlist and the input files are that commit’s. The PNG renders are high-resolution versions of the views shown in the Geometry section above.
Verilog netlist
module smart_toilet(
soln1,
soln2,
soln3,
out
);
input soln1, soln2, soln3;
output out;
wire connect01, connect02, connect0, connect1, connect2, connect3, connect5, connect6, connect31, connect32, connect33, connect34, connect35, connect36, connect37;
// Specification
serpentine_200px_0 serp1 (.in_fluid(soln2), .out_fluid(connect0));
serpentine_200px_0 serp1_1 (.in_fluid(connect0), .out_fluid(connect01));
serpentine_200px_0 serp1_2 (.in_fluid(connect01), .out_fluid(connect02));
serpentine_200px_0 serp2 (.in_fluid(connect02), .out_fluid(connect1));
diffmix_25px_0 mix0 (.a_fluid(soln1), .b_fluid(connect1), .out_fluid(connect2));
serpentine_300px_2 serp4 (.in_fluid(soln3), .out_fluid(connect3));
serpentine_300px_4 serp6 (.in_fluid(connect3), .out_fluid(connect31));
serpentine_300px_2 serp6_1 (.in_fluid(connect31), .out_fluid(connect32));
serpentine_300px_4 serp6_2 (.in_fluid(connect32), .out_fluid(connect33));
serpentine_300px_2 serp6_3 (.in_fluid(connect33), .out_fluid(connect34));
serpentine_300px_2 serp6_4 (.in_fluid(connect34), .out_fluid(connect35));
serpentine_300px_2 serp6_5 (.in_fluid(connect35), .out_fluid(connect36));
serpentine_300px_4 serp6_6 (.in_fluid(connect36), .out_fluid(connect37));
serpentine_300px_2 serp6_10 (.in_fluid(connect37), .out_fluid(connect5));
diffmix_25px_0 mix1 (.a_fluid(connect2), .b_fluid(connect5), .out_fluid(connect6));
serpentine_200px_0 serp7 (.in_fluid(connect6), .out_fluid(out));
endmodule